Dynamically Reconfigurable Dataflow Architecture

Abstract

In this thesis a dataflow architecture is introduced that maps efficiently onto multi-FPGA platforms and is composed of communication channels which can be dynamically adapted to the dataflow of the algorithm. The reconfiguration of the topology can be accomplished within a single clock cycle while DSP operations are in progress. Finally, the programmability and scalability of the proposed architecture is demonstrated on a parallel FFT implementation.

Summary

In recent years FPGA architectures have grown to be a competitive alternative for high performance DSP applications, previously dominated by ASIC devices and digital signal processors. However, FPGAs are characterized by a massive logical overhead in chip area due to their ability to be reconfigured, which results in poor clock rates. To overcome this problem, the foremost issue for FPGAs is the need to extract massive amounts of parallelism.

In this thesis a dataflow architecture is introduced that maps efficiently onto multi-FPGA platforms and is composed of communication channels which can be dynamically adapted to the dataflow of the algorithm. The main idea is based on reconfiguration. In contrast to the concept of partial reconfiguration that takes up to milliseconds, the approach presented here is to connect computational units through a dynamically variable topology. The latter consists of dedicated switches that can be individually updated within a single clock cycle. Thus, the proposed architecture combines the idea of reconfiguration with the performance of scalable parallel processing.

The dataflow between computational units is basically serial. However, a parallel extension for the dataflow channel width is also introduced. Similarly, the entire architecture is fully parameterized. Hence, beside the communication channel width, the number of connected computational units, the degree of virtualization and the number of interlinked FPGA devices can be selected to generate an application-specific optimal choice based on the available resources and the required computational DSP performance. Moreover, since the dataflow architecture is based on serial communication channels, the operand precisions can be arbitrarily chosen with no loss of scalability.

Another important aspect of modern DSP design is the need for system-level modeling. Correspondingly, in this thesis a programming model is introduced that abstracts the application programmer from RTL design.

Finally, the programmability and scalability of the dataflow architecture is demonstrated on a high-performance parallel FFT implementation. For this purpose a multi-FPGA platform has been developed, wherein dual- FPGA hardware boards are connected via high-speed optical transceivers operating with up to 3 Gbit/s.